The present invention relates generally to optoelectronic modules, and more specifically to techniques for maximizing optical coupling efficiency.
Much of the computer and communication networks being built today, including the Internet, are using fiber optic cabling. Fiber optic cabling data is transmitted using light signals, not electrical signals. For example, a logical one may be represented by a light pulse of a specific duration and a logical zero may be represented by the absence of a light pulse for the same duration. Since light is attenuated less in fiber than electrons traveling through copper, and multiple data streams can be transmitted at one time, the bandwidth of optic fiber is significantly greater than copper. Currently, networks continue to use fiber optics for transmitting data between nodes and silicon chips to process the data within nodes. Fiber optic transceivers, which convert light signals from a fiber optic cable into electrical signals, and vice versa, are used as the interface between a fiber optic line and a computer node.
FIG. 1 illustrates a perspective view of one example of an optoelectronic module 100 that can be used as an optical transceiver. Optoelectronic module 100 includes optical sub-assembly 102, which is mounted on top of chip sub-assembly 104. Optical sub-assembly 102 includes support block 103, which supports photonic devices 106 (laser emitters and light detectors). Chip sub-assembly 104 contains embedded semiconductor driver chip(s) and up-linking contacts on its top surface, which provides an electrical pathway to connect the semiconductor driver chip(s) to photonic devices 106. Electrical contact surfaces on the bottom surface of support block 103 can be connected to the up-linking contacts of chip sub-assembly 104 through a number of methods that include, for example, wire-stud bond with solder or conductive glue, wire-stud bond with anisotropic adhesive film, or solder. The remaining gap between optical sub-assembly 102 and chip sub-assembly 104 is filled with underfill material 105. Electrical traces on or in support block 103 connect photonic devices 106 to the electrical contact surfaces of support block 103. Optical fibers 108 are optically coupled to photonic devices 106 using various securing mechanisms (not shown). In the embodiment shown in FIG. 1, chip sub-assembly 104 is a Leadless Leadframe Package (LLP) having electrical contacts 110, which facilitate the connection of the module 100 to a substrate such as a printed circuit board. For more information regarding the optoelectronic module 100, refer to U.S. patent application Ser. No. 10/165,553 and U.S. patent application Ser. No. 10/165,711.
FIG. 2 illustrates a cross-sectional view of optoelectronic module 100 along line 2xe2x80x942 of FIG. 1. FIG. 2 shows that the electrical contacts on the bottom surface of OSA 102 are connected to the up-linking contacts of CSA 104 with solder balls 112. The relative orientation of OSA 102 and CSA 104 is shown to be in the most optimal configuration wherein the bottom surface of OSA 102 and the top surface of CSA 104 are parallel to each other. In this configuration, the mounted photonic devices 106 can be placed as close as possible to the optical fibers 108 for optimal optical coupling efficiency. Any misalignment and/or angular rotation in one of the sub-components (e.g., photonics, fiber ribbon, connector, OSA, etc.) will increase optical loss and adversely impact the module performance.
Unfortunately, optimal parallelism between OSA 102 and CSA 104 is not relatively easy to achieve. FIG. 3 illustrates a cross-sectional view of optoelectronic module 100 of FIG. 1 in the situation where parallelism between OSA 102 and CSA 104 is lost. The loss of parallelism is due, in part, to the fact that the current design of optoelectronic module 100 has the up-linking contacts of CSA 104 located near the forward edge (right side) of OSA 102. As a result, the connecting region is off the center of gravity of OSA 102. The imbalance can result in tilting of OSA 102 as shown in FIG. 3, where the left side of OSA 201 sinks into underfill 105 and solder balls 112 come to have different heights. The tilting of OSA 102 causes the loss of optical coupling efficiency and also can cause solder balls 112 to make contact with each other, thereby resulting in faulty electrical connections.
In view of the foregoing, a technique for maintaining the optical coupling efficiency between photonic devices of an optoelectronic module and its interconnecting optical fibers would be desirable.
The present invention pertains to techniques for maintaining the optical coupling efficiency between photonic devices of an optoelectronic module and its interconnecting optical fibers. The techniques ensure that the mating surfaces of an optical sub-assembly and a chip sub-assembly remain parallel with respect to each other throughout the soldering process of the optoelectronic manufacturing process.
One aspect of the invention pertains to a fixture used during the process of attaching an optical sub-assembly to a chip sub-assembly that includes a chip sub-assembly capture plate having a chip sub-assembly slot configured to support and secure the chip sub-assembly in a fixed orientation and having a set of index holes, and an optical sub-assembly capture plate having an optical sub-assembly slot configured to align and maintain the relative orientation between the optical sub-assembly and a chip sub-assembly such that the bottom surface of the optical sub-assembly and the top surface of the chip sub-assembly are substantially parallel.
Another aspect of the invention pertains to an optoelectronic manufacturing system that includes a molded leadframe panel that includes a metal leadframe panel that supports a molded resin panel, the molded resin panel containing an embedded array of chip sub-assemblies, and a fixture panel mounted on top of the molded leadframe panel. The fixture panel includes a first optical sub-assembly securing plate having a plurality of openings configured to fit around the perimeter of a respective optical sub-assembly, and a second optical sub-assembly securing plate having a plurality of openings configured to fit around the perimeter of a respective optical sub-assembly at a region above the first optical sub-assembly securing plate.
Another aspect of the present invention pertains to a method for maintaining the relative orientation between an optical sub-assembly and a chip sub-assembly during assembly. The method comprises providing a chip sub-assembly capture plate having a chip sub-assembly slot, inserting a chip sub-assembly into the chip sub-assembly slot, the chip sub-assembly slot configured to support and secure the chip sub-assembly in a fixed orientation, providing an optical sub-assembly capture plate having an optical sub-assembly slot, inserting an optical sub-assembly into the optical sub-assembly slot, the chip and optical sub-assembly capture plates cooperatively configured to align and maintain the relative orientation between the optical sub-assembly and a chip sub-assembly such that the bottom surface of the optical sub-assembly and the top surface of the chip sub-assembly are substantially parallel, and placing the combination of the chip and optical sub-assembly capture plates and the chip and optical sub-assemblies into a reflow oven to undergo a reflow process.
Another aspect of the invention pertains to an optoelectronic module that includes a chip sub-assembly, an optical sub-assembly, and a high-temperature tape positioned on the top surface of the molded resin package and supporting at least a portion of the bottom surface of the optical sub-assembly such that the bottom surface of the optical sub-assembly and the top surface of the molded resin package are substantially parallel.
Another aspect of the invention pertains to a semiconductor leadframe panel that includes an electrically conductive substrate having a molded resin panel formed thereon, an array of semiconductor dice encapsulated within the molded resin panel, the top surface of each semiconductor die supporting at least one up-linking contact such that an up-linking contact surface of each up-linking contact is exposed through a top surface of the molded resin panel, and a plurality of high-temperature tape strips adhered to the top surface of the molded resin panel and positioned adjacent to each row of up-linking contact surfaces. A method for using the high temperature tape with a leadframe panel is also described.
Yet another aspect of the invention pertains to an optoelectronic module that includes a semiconductor chip sub-assembly having a top surface that includes a plurality of up-linking contact surfaces, and a support block having at least one pedestal extending from the bottom surface of the support block, the pedestal configured to support the support block in an orientation in which the bottom surface of the support block is substantially parallel with the top surface of the chip sub-assembly.